{
	"title": "Intel(R) Core(TM)2 Extreme Processor QX9650, PCN 108231-01, Product Design, C-0 to C-1 Stepping Conversion, Reason for Revision: Adjust the Customer Ready to Receive Date to August 4, 2008",
	"id": "806769",
	"created_at": "2023-12-21T07:50:57+00:00",
	"modified_at": "2008-04-03T00:00:00+00:00",
	"description": "Desktop Processors, Product Design, Customers may want to perform re-qualification, re-test, re-certification or standard validation testing for this change; see sample detail in PCN where applicable.",
	"download_url": "https://cdrdv2-public.intel.com/806769/PCN108231-01.pdf",
	"html_url": "https://intel.com/content/www/us/en/content-details/806769/intel-r-core-tm-2-extreme-processor-qx9650-pcn-108231-01-product-design-c-0-to-c-1-stepping-conversion-reason-for-revision-adjust-the-customer-ready-to-receive-date-to-august-4-2008.html",
	"url": "https://intel.pcn.captnemo.in/pcn/806769",
	"category": "Product Change Notifications (PCN)",
	"self": "https://intel.pcn.captnemo.in/api/806769.json"
}